Split gate non-volatile flash memory cells having a select gate, a floating gate, a control gate and an erase gate are well known in the art. See for example U.S. Pat. No. 6,747,310. An erase gate having an overhang over the floating gate is also well know in the art. See for example, U.S. Pat. No. 5,242,848. Both of the foregoing disclosures are incorporated herein by reference in their entirety.
Heretofore, the prior art has failed to teach or disclose that an overhang of the erase gate to the floating gate within certain limitations enhances the erase efficiency.
Accordingly, it is one of the objectives of the present invention to improve the erase efficiency of such a cell by certain dimensional relationship between the erase gate and the floating gate.